• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    An information transmission method with error correction for user words, an error correcting decoding method for such user words, an apparatus for information transmission for use with the method, a device for information decoding for use with the method, and an apparatus for use with such device. There is described a method and apparatus for error correcting data transmission between a user device and a medium. The information integrity is maintained by a first and second cross-interleaved Reed-Solomon code. A third Reed-Solomon code is overlaid on the CIRC code in that a sector is built from user words and protected by a quasi- product code. Then an encoded sector is divided into groupts, which are group-wise presented to the CIRC encoder.
    公开号:SU1505451A3
    申请号:SU853874714
    申请日:1985-03-22
    公开日:1989-08-30
    发明作者:Сузуки Тадао；Сако Иоширо；Фурукава Шунске；Фуруайа Тсунео
    申请人:Н.В.Филипс Глоэлампенфабрикен (Фирма)；
    IPC主号:
    专利说明:

    one
    (21) 3874714 / 24-24
    (22) 03.22.85
    (31) 57595/84; 57596/84
    (32) 03/24/84
    (33) JP
    (46) 08/30/89, Vul. Number 32
    (71) N.V. Phillips Gloelampenfabriken (NL)
    (72) Tadao Suzuki, Yoshiro Sako, Shunske Furukawa and Tsuneo Furuaya
    (JP)
    (53) 681.32 (088.8)
    (56) USSR author's certificate
    No. 675612, cl. H 04 L 1/10, 1978.
    Patent of the USSR No. 1271382, cl. G 08 C 19/28, 1981.
    (54) DEVICE FOR DECODING
    tAI INFO with ERROR FIX
    (57) The invention relates to automation and computing and can be used in CDs for optical reading of high-quality audio information or for storing digital data. The purpose of the invention is to increase the noise immunity of the device. A device for decoding information with Error Correction contains a demodulator 1, a demultiplexer 2, a delay block 3, a Reed-Solomon proverbial 4 decoder, a block of 5 delay elements, a word by word
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    Reed-Solomon decoder 6, delay unit 7, proverbial memory block 8, Reed-Solomon pseudo-production decoder 9, 10 error detector, device input 11, control output 12, insufficient correction output 13 and device information outputs 14.
    The invention relates to automation and computing and can be used in CDs for optical reading of high-quality audio information.
    The purpose of the invention is to improve the noise immunity of the device.
    Figure 1 shows the data format on a compact optical disc; Fig. 2 illustrates an error correction decoding device d11; in FIG. 3a, a format of a semantic information block for explaining (de) a coding organization; fig.Zb - the same option; Fig. 4 shows the principle layout of one sector based on bit units; Fig. 5 illustrates the principle layout of one sector based on words; Figures 6 and 7 show principle diagrams for explaining the dependence of alternations in one sector.
    A device for decoding an error-correcting formation includes a demodulator 1, a demultiplexer 2 a delay unit 3, a Reed-Solomon word processor 4, a delay unit 5, a Reed Solomon word processor 6, a delay unit 7, a memory block 8, a reed decoder 9 Solomon pseudoproduction, 10 error detector, device input 11, control output 12, insufficient correction output 13 and device information outputs 14.
    The data format can be described on the example of a CD. The proposed device can also be used with each other of the parameters of the format, in particular, the number of bits in a symbol, the number of symbols in the sector, or I HKJie or the number of parity symbols, up to 11 SLS1 Hohs at successive stages, can be different. .
    The cycle (Fig. 1) contains 588 recorded and 1 H1 channel bits. Every peak
    The hypothesis of isofethenia is that the pair of cross-striped Reed-Solomon is supplemented with a code of further protection against an error, in which all processing is performed in characters of relatively short duration of 8 bits. 7 il.
    0
    0
    five
    5 5
    0 5
    starts with a 24 bit sync structure. The synchronization structure, as well as all additional information symbols, are placed in front of groups of three so-called merging bits (dimmed) that are added; y1 decreases the DC component of the recorded signal. The symbol P is called the user-encoded bit group. This code can be used to control the read from the disk to display information relating to the content, such as time and addresses on a video display, or for other purposes. Each recorded or recorded symbol consists of fourteen channel bits, which, when modulated, are formed from code bits, and the code bits during demodulation must again be regrouped.
    The decoding apparatus of FIG. 2, for use with the format of FIG. 1, operates as follows.
    The channel symbols are fed to the input 11 in the form of consecutive bits. In the demodulator 1, the first serial-parallel conversion occurs. Then 24-bit channel. the character is converted to an eight-bit character. The eight-bit code symbol is fed to the input of the demultiplexer 2. Under certain circumstances, -; In addition, additional flag information may be supplied to this input to demonstrate the impossibility or doubtfulness of the conversion. Merging bits may or may not be taken into account for determining flag information. Simultaneous control can be demodulated in the same way as other symbols.
    515
    The delay unit 3 delays characters received during one frame interval. At the output of decoder 4, for each of the 32 received symbols, there is a group of 28 issued symbols. If necessary, each symbol can be equipped with its own flags or flags of reliability. Block 5 enter
    9
    appropriate delays to ensure non-interleaved mode. Each block element introduces a delay expressed in a number of cycle intervals. The first element introduces a delay at four such intervals, the second at eight intervals, and so on. With a pulsed error in the medium, such a pulse affects a large time interval, as a result of which each newly formed group contains only a limited number of errors.
    Decoder 6 corrects a group of 28 received symbols with the first Reed-Solomon code. Thus, at the output of decoder 6, for each group of 28 received symbols, there is a group of 24 issued symbols. If necessary, each issued symbol can again be equipped with its own flag or reliability flags. Block
    7 introduces appropriate delays for the introduction of a de-interleaved mode. The delay occurs over two cycle intervals. Certain sequential rearrangement of symbols occurs within the cycle. When using sound devices, the interleaving mode provides better possibilities for damping the effects
    formed by invalid characters
    In this case, the odd symbol and its even receiver together form a 16-bit sound sample.
    Block 8 is a memory device for corrected characters along with associated flag information. These symbols are stored as long as there is a so-called spector. The decoder 9 is intended for decoding and, if available, for correcting sector information. The corrected user characters are then supplied to the user device.
    Fig. 3 shows a combination of 98 consecutive cycles received at input 11 (Fig. 2), where each cycle closes one line. Due to
    0
    five
    0
    five
    0
    five
    0
    five
    0
    five
    the combined effect of blocks 3, 5 and 7 of the delay is not consistent with the actual content of the sector. The merging bits are not shown as it is assumed that demodulation has occurred. The first column shows 98 consecutive FS synchronization structures, secondly, DB (0) is the content of the symbol O of the cycle, the third contains the content of data symbols 1-12, 17-28 of the cycle, the fourth contains the content of eight parity characters RB with each cycle . In a sound system, 24 data symbols of each cycle form six stereo samples of 2x16 bits each. In the zero and first cycles, the sub-character (column DB (0)) forms the sync structure SYNCPAT, which has a specified format and is used to perform synchronization for the sub-code at the sector level.
    In accordance with the format of the CD, channel P (the combined first bit of consecutive characters of the subcode from the second to the 97th frame) forms a flag that distinguishes the music program and pause. It has a low level during a music program, a high level during a pause, and switches to a frequency of 2 Hz in the output sector. In this connection, you can select a specific music by counting this signal. Channel Q further expands this type of control. If the Q channel information is stored in a disk player microcomputer, then switch from one language program to another to perform a certain random sampling with an accuracy of 145 seconds. P and W channels can contain digit-encoded speech as additional information for the audio signal.
    In the Q column, the first two bits are used for synchronization in SYNCPAT, the following four bits are used as control bits, the next four bits are used as address bits, the next 72 bits are used as data bits. These bits can include the next TNR numeric code and the X index code. Both codes can vary from the decimal number 00 to the decimal number 99. Other data includes a time indication code that defines the duration of the music program and
    pauses, efficiency time of the day, defining the abs. Piece length of the run from the front. I D end of the program area of the CD. These time display codes define minutes, seconds, and cycles in decimal digits. One second is divided into 75 cycles. To access a compact disc based on a unit that is shorter than a music program, for example in digital data, the specified absolute time code is used as an address. The last sixteen bits of the Q channel are used for the error detection code using the ATP check.
    In this embodiment, when digital data is recorded as DB data, the format of the sub-coding channels G and Q is the same as in the CD system. After decoding the first and second Reed-Solomon codes and the deinterlacing in block 7, the data is grouped into a sector. The sector length corresponds to the user information of 98 frames, which is 2352 bits. Fig. 3a shows the function of the corresponding sector elements. A sector contains a sector synchronization signal from 12 Siths, information from 4 bits, a 2048 user bits, an EDC error detection code of four bits, based on the CRC principle (it should not be confused with the 16-bit CRC code in the Q channel, fig.3, an interval of 8 bits dp for further expansion of the function, 172 bits of parity P and 104 bits of parity Q of the third Reed-Solomon code. General information of one sector can be selected together in the decoder.
    Figure 4 shows the location of one sector, Levyts and the right channels correspond to the sample data in the left and right channels of the stereo sound data. In each channel, one word consists of 16 bits, L is the smallest significant bit, M is the largest significant bit. For 6x2x2 stereo audio data, 24 bits are recorded in the interval specified by the cycle sync signal. Therefore, when recording digital data, the same signal format (phpg, 1) in the form of stereo audio data is recorded in one sector (2352 bits) 0-97 cycles, since they are permeuropane and in accordance with the content of the subcode (subcode-cycles). Thus, the digital data of the DB sector has a DLS1U corresponding to the interval between days of the zero-cycle sequential synchronization patterns (SYNCPAT) of the sub-code signal, Interlace} I1 between different sectors does not occur.
    The first bit of the sector's digital data has all the bits O, the next 10 bits all the bits 1, the twelfth bit all the bits O. The DTOT 12-bit interval is the sector clock signal, showing a 111D1y sector header. After the sector clock signal, the upper parts refer to MIN minutes, SEC seconds, SECT sector and MOD mode, each of which consists of one bit. These headers are addresses of one sector and 75 sectors correspond to one second, like a subcode loop. Mode data shows the type of sector data. In FIG. 4, D0001 to D2336 are the sector bit numbers, including the sector synchronization signal and the headers, D0001 to D2048 are for user data, D2049 to D2052 for error detection code, D2053 to D2060 for interval, D2061 to D2232 for dl parity P and D2233 - D2336 - for parity Q,
    Fig. 5 shows the location of one sector, expressed as words: 1) 000 and D0001 - for headers, D0002 - D1025 - for user data, D1026 and D1027 - for an error detection code, D1023 - D1031 .- for an interval, D1032 - D1117 for parity P and D1118 - D1169 for parity Q. The error detection code includes the header and user data (DOOOO - D1027), as well as 12 synchronization bits. The error detection code includes the header and user data (DOOOO - D1027), as well as the parity P and the parity Q, the CRC bits and the interval 118, but not the sync bits.
    The CRC code that is used as the error detection code has, for example, the following generating polynomial g (x):
    B (x) +1) (x xx + x + 1),
    The CRC code is a binary code with characters from the CF field (28). This error detection code is used to check final reliability after error correction. This check can be performed as by decoding with codes
    recoding of i1 / ia-C oJioMOH and using pseudo-code based on Reed-Solomon sector. Thus, the CRC code; should signal an incorrect fix in the user device,
    Each word of the WOOOO-W1169 sector is divided into two bits: the largest and the least significant. P1a and large significant 1170 bits are grouped in the second data plane. Sector-based errors are performed for each of these data planes separately. However, the decoding for the corresponding data planes is the same.
    FIG. 6 is a diagram for explaining coding over any data plane. The data plane consists of 1032 bits, containing a header and user data, CRC, interval data. These 1032 bits in meaning are like a matrix of 24x43 bits. For convenience, bits are indicated by the number of the corresponding word. These sector-organized bits encode in another group of two Reed-Solomon codes. The matrix image shows the sequential organization of the last two codes in different directions of the matrix.
    Further, in accordance with the columns of FIG. 6, the following Reed-Solomon code is used. This code has a code word length of 26 characters and a so-called size of 24 characters. The corresponding parity symbols P are shown in rows 24 and 25, the Corresponding Halois field P F can be generated using the primitive polynomial P (x) x x + x + x + 1,
    The corresponding primitive element is 00000010, with the last bit being the least significant. The generator for the code is given by product (x-a) (x-a), the HP parity check matrix for this code is as follows: 1 11 1 1
    HP
    g
    , r4
    ;
    If it is accepted that, after decoding, the P series is UR, then the parity symbols will be D (43x24 + NP) and PUr (3x25 + NP) (NP 0,1,2 ,, .., 41,42), which correspond to The following erasure:
    IIP X HS O,
    5451
    TO)
    Where
    0
    five
    0 (43x0 + NP);
    D (43x1 + NP);
    D (43x2 + NP);
    (43xMP-t-NP),
    D (43x24 + NP),
    D (43x25 + NP) ,, ,,.,. 42; ,,,, 25.
    For example, if one reproducible parity P is generated with HOOO, Yu043, D0086, D0129, D0172 ,,,, D0946, D0989, D1032 (PO), D1075 (P1), which are located in the first column.
    The other Reed-Solomon code is used in a diagonal direction, as indicated by the QSEC arrow in FIG. 6. This code has a code word length of 45 bits or characters and a size of 43 characters. The corresponding parity symbols, O, are shown in two rows of QPARs. In this case, there are 26x2 parity symbols (as many pairs as there are user symbols in any column. The polynomial P (x) is the same, and the parity check matrix is as follows:
    HP
    one
    "four
    one
    one
    -15
    , 42
    ,one

    35
    40
    45
    50
    55 If the reproduced Q series is YQ, then the parity symbols (43x26 9NQ) and Q1 D (44x26-t-NQ) answer the following equation:
    HP X YQ O, where D (44 X O +43 x NQ);
    D (44 X 1 + 43 X NQ);
    D (44 X 2 + 43 X NQ); (44 X MQ + 43 x NQ),
    D (44 X 40 + 43x NQ);
    D (44x41 + 43 X NQ);
    D (44 X 42 + 43 + NQ);
    D (44 X 26 + NQ);
    D (44 X 26 + NQ),
    If we accept that (, 1,2,3 ,,. ,, 24,25) and (, 1,2,3 ,,,, 41,42), and if (44 X MQ + 43 x NQ) 1117, (A4xMQ + +43 X NQ) can be calculated as (44xM + 43xN-1118),
    Fig. 7 corresponds to Fig. 6; In Fig. 6, the column is turned up by one position, for two by two positions, etc. Simulation parity O is shown in two additional columns. Rows in FIG. 7 form their own series O,
    15
    Each column forms (currently rotated) the P series, with the exception of the QO, Q1 columns. In connection with this, FIG. 7 shows the location of the quasi-code with the use of (26,24) Reed-Solomon code in the vertical direction and (45,43) Reed-Solomon code in the horizontal direction.
    Since each of the two Reed-Solomon codes has two parity symbols even in the absence of an error flag, one character error can be corrected in each code sequence. When the location of the error is known by the error flag, two character errors can be corrected. This error flag can be obtained by decoding the first and second Reed-Solomon kodos. By alternately decoding the Reed-Solomon code in the vertical direction (as decoding P) and decoding the Reed Solomon code in the horizontal direction of the SRI (Q decoding), for example, by performing decoding Q, decoding P, decoding Q, all error structures that are have a maximum of two errors indicated by the symbol flags for any P series or Q series, which can be reduced by the initial processing. The simplest structure itself, which cannot be corrected, has three P series with three error symbols in each, and the error symbols are found 3x3 only in the third Q series. Additional errors worsen the situation even more.
    Coding is performed for two
    data planes (containing the largest significant and smallest significant bits, respectively) are similar. The coding is performed with lltB header words and user data, CRC control bits, and one sector sector bits.
    Q
    0 5 Q
    five
    0
    five
    12
    权利要求:
    Claims (1)
    [1]
    After encoding, the corresponding data planes are synthesized and the sector synchronization signal is added in such a way that the location of one sector shown in FIGS. 4 and 7 is obtained. This sector is fed to the CD CIRC decoding. Invention Formula
    A device for decoding error correction information containing a first delay unit, the outputs of which are connected to the same inputs of the first word-by-word Reed-Solomon decoder, the outputs of the first word-by-word Reed-Solomon decoder through the corresponding elements of the second delay unit are connected to the same-name inputs of the second word-by-word Reed decoder Solomon, the first and second outputs of which are connected to the same inputs of the third delay unit, characterized by the fact that it is h -o, in order to increase the noise immunity of the device, into it the memory block, the third pseudo-Reed-Solomon decoder, the error detector, the demultiplexer and the demodulator, the first outputs of which are connected to the inputs of the demultiplexer, the outputs of which are connected to the same inputs of the first delay block, are entered, the first and second outputs of the third block of the delay are connected to the same ones the memory unit inputs, the first and second memory unit inputs-outputs are connected to the same outputs-inputs of the third pseudo-Reed-Solomon decoder, the outputs of which are information outputs stroystva, input and a second output of the demodulator are respectively input and output of the control device, the third output of the memory unit is connected to the input of the error detector, the output of which is output il insufficient correction device.
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    类似技术:
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    同族专利:
    公开号 | 公开日
    AU584883B2|1989-06-08|
    GB2156555A|1985-10-09|
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    EP0156440B1|1990-01-24|
    CZ8502009A3|1996-09-11|
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    DE3575646D1|1990-03-01|
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    CA1255771A|1989-06-13|
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    FR2561839B1|1987-11-13|
    US4680764A|1987-07-14|
    AU4024085A|1985-09-26|
    GB8507248D0|1985-04-24|
    KR940008742B1|1994-09-26|
    KR850006950A|1985-10-25|
    CZ281601B6|1996-11-13|
    USRE33462E|1990-11-27|
    HK43393A|1993-05-14|
    EP0156440A3|1986-12-30|
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    申请号 | 申请日 | 专利标题
    JP59057595A|JPH07101543B2|1984-03-24|1984-03-24|Error correction coding method|
    JP59057596A|JPH0687348B2|1984-03-24|1984-03-24|Digital data transmission method|
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